1. Field of the Invention
The present invention relates to a metal oxide semiconductor (MOS)-type semiconductor device, and more particularly, to a low substrate noise MOS-type semiconductor device.
2. Description of the Related Art
In a complementary MOS analog/digital hybrid large scale integrated (LSI) device, digital circuits where voltages are fully swung and analog circuits where a very small voltage less than some mV is significant are mixed. Therefore, noise easily penetrates from the digital circuits via power supply lines and a substrate to the analog circuits.
The noise from the digital circuits via the power supply lines to the analog circuits can be reduced by providing individual power supply lines for the digital circuits and the analog circuits, an approach which has been broadly used.
On the other hand, the noise, so called substrate noise, from the digital circuits via the substrate to the analog circuits is generated from a 1-bit output delta-sigma modulator or a charge pump circuit of a phase locked loop (PLL) circuit. In a CMOS device, if an N-channel MOS transistor is formed in a P-type semiconductor substrate, a P-channel MOS transistor is formed in an N-type well. In this case, the back gate of the N-channel MOS transistor is the substrate and the back gate of the P-channel Mos transistor is the well. Since the well is separated from the substrate by a PN junction therebetween and an analog power supply voltage is applied to the well, the P-channel MOS transistor hardly suffers from the substrate noise. Conversely, the N-channel MOS transistor suffers directly from the substrate noise.
In a prior art semiconductor device, in order to suppress the substrate noise, an impurity diffusion region, i.e., a substrate contact region, of the same conductivity type as the substrate having a higher impurity concentration than the substrate is formed in the substrate to surround a transistor area. Also, the substrate contact region is connected to a definite power supply voltage line. Thus, the voltage in the substrate around the transistor area is brought close to the voltage at the power supply voltage line, thus reducing the substrate noise. This will be explained later in detail.
In the above-described prior art semiconductor device, however, the devices have become increased in size, thus increasing the substrate noise and reducing the impedance of noise sources, so that the power supply line connected to the substrate contact region per se suffers from the substrate noise. Also, this power supply line serves as a noise source for other transistor areas. Further, since individual power supply voltages are applied to the source region and the substrate contact region, noises superimposed onto the power supply voltages are added to a current of the transistor as a noise current
Also, in the prior art semiconductor device, in order to increase the integration, the width of the substrate contact region is so reduced that the resistance of the substrate contact region and its neighborhood is increased. As a result, the resistance between the back gate and the substrate contact region is not so small as the resistance between the back gate and the substrate, and accordingly, the substrate noise can be reduced by the substrate contact region to only about 1/2.
Further, usually, a channel stopper region is provided to surround the substrate contact region, to thus avoid the creation of a parasitic MOS transistor. However, since the substrate contact region serves as a low impedance for noise transmitted via the channel stopper, the substrate noise cannot be further suppressed.